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Rev. 1.01, Nov. 2010 K4B1G0446G K4B1G0846G
1Gb G-die DDR3 SDRAM
78FBGA with Lead-Free & Halogen-Free (RoHS compliant)
datasheet
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K4B1G0446G K4B1G0846G
datasheet
History - First release. - Corrected Typo. Draft Date Nov. 2010 Nov. 2010
Rev. 1.01
DDR3 SDRAM
Revision History
Revision No. 1.0 1.01 Remark Editor S.H.Kim S.H.Kim
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
Table Of Contents
1Gb G-die DDR3 SDRAM
1. Ordering Information ..................................................................................................................................................... 5 2. Key Features................................................................................................................................................................. 5 3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6 3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6 3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7 3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8 4. Input/Output Functional Description.............................................................................................................................. 9 5. DDR3 SDRAM Addressing ........................................................................................................................................... 10 6. Absolute Maximum Ratings .......................................................................................................................................... 11 6.1 Absolute Maximum DC Ratings............................................................................................................................... 11 6.2 DRAM Component Operating Temperature Range ................................................................................................ 11 7. AC & DC Operating Conditions..................................................................................................................................... 11 7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11 8. AC & DC Input Measurement Levels ............................................................................................................................ 12 8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12 8.2 VREF Tolerances...................................................................................................................................................... 13 8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 14 8.3.1. Differential signals definition ............................................................................................................................ 14 8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14 8.3.3. Single-ended requirements for differential signals ........................................................................................... 15 8.4 Differential Input Cross Point Voltage...................................................................................................................... 16 8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16 8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16 9. AC & DC Output Measurement Levels ......................................................................................................................... 17 9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17 9.2 Differential AC & DC Output Levels......................................................................................................................... 17 9.3 Single-ended Output Slew Rate .............................................................................................................................. 17 9.4 Differential Output Slew Rate .................................................................................................................................. 18 9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18 9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19 9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19 9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19 9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20 9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21 9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21 9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 22 9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 23 9.9 ODT Timing Definitions ........................................................................................................................................... 24 9.9.1. Test Load for ODT Timings .............................................................................................................................. 24 9.9.2. ODT Timing Definitions .................................................................................................................................... 24 10. IDD Current Measure Method..................................................................................................................................... 27 10.1 IDD Measurement Conditions ............................................................................................................................... 27 11. 1Gb DDR3 SDRAM G-die IDD Specification Table .................................................................................................... 36 12. Input/Output Capacitance ........................................................................................................................................... 37 13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 ...................................................................... 38 13.1 Clock Specification ................................................................................................................................................ 38 13.1.1. Definition for tCK(avg).................................................................................................................................... 38 13.1.2. Definition for tCK(abs).................................................................................................................................... 38 13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 38 13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 38 13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38 13.1.6. Definition for tERR(nper) ................................................................................................................................ 38 13.2 Refresh Parameters by Device Density................................................................................................................. 39 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39 13.3.1. Speed Bin Table Notes .................................................................................................................................. 43
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
14. Timing Parameters by Speed Grade .......................................................................................................................... 44 14.1 Jitter Notes ............................................................................................................................................................ 50 14.2 Timing Parameter Notes........................................................................................................................................ 51 14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 52 14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 59
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K4B1G0446G K4B1G0846G
datasheet
DDR3-1066 (7-7-7) K4B1G0446G-BCF8 K4B1G0846G-BCF8 DDR3-1333 (9-9-9)4 K4B1G0446G-BCH9 K4B1G0846G-BCH9 DDR3-1600 (11-11-11)3 K4B1G0446G-BCK0 K4B1G0846G-BCK0
Rev. 1.01
DDR3 SDRAM
1. Ordering Information
[ Table 1 ] Samsung 1Gb DDR3 G-die ordering information table Organization 256Mx4 128Mx8 DDR3-1866 (13-13-13)2 K4B1G0446G-BCMA K4B1G0846G-BCMA Package 78 FBGA 78 FBGA
NOTE : 1. Speed bin is in order of CL-tRCD-tRP. 2. Backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7) 3. Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) 4. Backward compatible to DDR3-1066(7-7-7)
2. Key Features
[ Table 2 ] 1Gb DDR3 G-die Speed bins Speed tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) DDR3-800 6-6-6 2.5 6 15 15 37.5 52.5 DDR3-1066 7-7-7 1.875 7 13.125 13.125 37.5 50.625 DDR3-1333 9-9-9 1.5 9 13.5 13.5 36 49.5 DDR3-1600 11-11-11 1.25 11 13.75 13.75 35 48.75 DDR3-1866 13-13-13 1.07 13 13.91 13.91 34 47.91 Unit ns nCK ns ns ns ns
* JEDEC standard 1.5V 0.075V Power Supply * VDDQ = 1.5V 0.075V * 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin 900MHz fCK for 1866Mb/sec/pin * 8 Banks * Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13 * Programmable Additive Latency: 0, CL-2 or CL-1 clock * Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866) * 8-bit pre-fetch * Burst Length: 8 (Interleave without any limit, sequential with starting address "000" only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] * Bi-directional Differential Data-Strobe * Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) * On Die Termination using ODT pin * Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95 C * Asynchronous Reset * Package : 78 balls FBGA - x4/x8 * All of Lead-Free products are compliant for RoHS * All of products are Halogen-free
The 1Gb DDR3 SDRAM G-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR31866) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V 0.075V power supply and 1.5V 0.075V VDDQ. The 1Gb DDR3 G-die device is available in 78ball FBGAs(x4/x8).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in "DDR3 SDRAM Device Operation & Timing Diagram". 2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
3. Package pinout/Mechanical Dimension & Addressing
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package
1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS
2 VDD VSSQ DQ2 NC VDDQ VSS VDD CS BA0 A3 A5 A7 RESET
3 NC DQ0 DQS DQS NC RAS CAS WE BA2 A0 A2 A9 A13
4
5
6
7 NC DM DQ1 VDD NC CK CK A10/AP NC A12/BC A1 A11 NC
8 VSS VSSQ DQ3 VSS NC VSS VDD ZQ VREFCA BA1 A4 A6 A8
9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS A B C D E F G H J K L M N
1
2
3
4
5
6
7
8
9
Ball Locations (x4)
A B C
Populated ball Ball not populated
D E F G H
Top view (See the balls through the package)
J K L M N
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package
1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS
2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET
3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13
4
5
6
7 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 NC
8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8
9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS A B C D E F G H J K L M N
Ball Locations (x8)
1 A B C
2
3
4
5
6
7
8
9
Populated ball Ball not populated
D E F G H
Top view (See the balls through the package)
J K L M N
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
3.3 FBGA Package Dimension (x4/x8)
Units : Millimeters
7.50 0.10
A 3.20 #A1 INDEX MARK B
(Datum A)
0.80
1.60
987654321 A B C D E F G H J K L M N (0.30) MOLDING AREA (0.60)
0.80
4.80
(Datum B)
0.80 x 12 = 9.60
78 - 0.48 Solder ball (Post Reflow 0.50 0.05) 0.2 M A B
BOTTOM VIEW
0.80
11.00 0.10
#A1
7.50 0.10
11.00 0.10
0.10MAX 0.37 0.05 1.10 0.10
TOP VIEW
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K4B1G0446G K4B1G0846G
datasheet
Type Input Function
Rev. 1.01
DDR3 SDRAM
4. Input/Output Functional Description
[ Table 3 ] Input/Output function description Symbol CK, CK Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode Register Set commands. Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. Data Input/ Output: Bi-directional data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/ x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. No Connect: No internal electrical connection is present. Supply Supply Supply Supply Supply Supply Supply DQ Power Supply: 1.5V +/- 0.075V DQ Ground Power Supply: 1.5V +/- 0.075V Ground Reference voltage for DQ Reference voltage for CA Reference Pin for ZQ calibration
CKE
Input
CS
Input
ODT
Input
RAS, CAS, WE DM (DMU), (DML)
Input Input
BA0 - BA2
Input
A0 - A13
Input
A10 / AP
Input
A12 / BC
Input
RESET DQ
Input Input/Output
DQS, (DQS)
Input/Output
TDQS, (TDQS)
Output
NC VDDQ VSSQ VDD VSS VREFDQ VREFCA ZQ
NOTE : Input only pins (BA0-BA2, A0-A13, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
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K4B1G0446G K4B1G0846G
datasheet
256Mb x 4 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9,A11 A12/BC 1 KB 128Mb x 8 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 1 KB
Rev. 1.01
DDR3 SDRAM
5. DDR3 SDRAM Addressing
1Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 64Mb x 16 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9 A12/BC 2 KB
2Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 512Mb x 4 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9,A11 A12/BC 1 KB 256Mb x 8 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 1 KB 128Mb x 16 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 2 KB
4Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size
*1
1Gb x 4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 1 KB
512Mb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 1 KB
256Mb x 16 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 2 KB
8Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size
*1
2Gb x 4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11,A13 A12/BC 2 KB
1Gb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 2 KB
512Mb x 16 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 2 KB
NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG/8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
6. Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -55 to +100 Units V V V C NOTE 1,3 1,3 1 1, 2
NOTE : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range
[ Table 5 ] Temperature Range Symbol TOPER Parameter Operating Temperature Range rating 0 to 95 Unit C NOTE 1, 2, 3
NOTE : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
7. AC & DC Operating Conditions
7.1 Recommended DC operating Conditions (SSTL_1.5)
[ Table 6 ] Recommended DC Operating Conditions Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.5 1.5 Max. 1.575 1.575 Units V V NOTE 1,2 1,2
NOTE : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address Symbol Parameter DDR3-800/1066/1333/1600 Min. VREF + 100 VSS VREF + 175 Note 2 VREF+150 Note 2 0.49*VDD Max. VDD VREF - 100 Note 2 VREF - 175 Note 2 VREF-150 0.51*VDD Min. VREF + 100 VSS VREF + 135 Note 2 VREF+125 Note 2 0.49*VDD DDR3-1866 Max. VDD VREF - 100 Note 2 VREF - 135 Note 2 VREF-125 0.51*VDD Unit mV mV mV mV mV mV mV mV mV mV V NOTE 1,5 1,6 1,2,7 1,2,8 1,2,7 1,2,8 1,2,7 1,2,8 1,2,7 1,2,8 3,4
VIH.CA(DC100) DC input logic high VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VIH.CA(AC135) VIL.CA(AC135) VIH.CA(AC125) VIL.CA(AC125) VREFCA(DC) DC input logic low AC input logic high AC input logic low AC input logic high AC input logic low AC input logic high AC input logic low AC input logic high AC input logic low Reference Voltage for ADD, CMD inputs
NOTE : 1. For input only pins except RESET, VREF = VREFCA(DC) 2. See 'Overshoot/Undershoot Specification' on page 19. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference : approx. 15mV) 4. For reference : approx. VDD/2 15mV 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is used when VREF + 150mV is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used when VREF - 150mV is referenced.
[ Table 8 ] Single-ended AC & DC input levels for DQ and DM Symbol Parameter DDR3-800/1066 Min. VREF + 100 VSS VREF + 175 NOTE 2 VREF + 150 NOTE 2 0.49*VDD Max. VDD VREF - 100 NOTE 2 VREF - 175 NOTE 2 VREF - 150 0.51*VDD DDR3-1333/1600 Min. VREF + 100 VSS VREF + 150 NOTE 2 0.49*VDD Max. VDD VREF - 100 NOTE 2 VREF - 150 0.51*VDD DDR3-1866 Min. VREF + 100 VSS VREF + 135 NOTE 2 0.49*VDD Max. VDD VREF - 100 NOTE 2 VREF - 135 0.51*VDD Unit mV mV mV mV mV mV mV mV V NOTE 1,5 1,6 1,2,7 1,2,8 1,2,7 1,2,8 1,2,7 1,2,8 3,4
VIH.DQ(DC100) DC input logic high VIL.DQ(DC100) DC input logic low VIH.DQ(AC175) AC input logic high VIL.DQ(AC175) AC input logic low VIH.DQ(AC150) AC input logic high VIL.DQ(AC150) AC input logic low VIH.DQ(AC135) AC input logic high VIL.DQ(AC135) AC input logic low VREFDQ(DC) Reference Voltage for DQ, DM inputs
NOTE : 1. For input only pins except RESET, VREF = VREFDQ(DC) 2. See 'Overshoot/Undershoot Specification' on page 19. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference : approx. 15mV) 4. For reference : approx. VDD/2 15mV 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used when VREF + 150mV is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when VREF - 150mV is referenced.
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K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on page 12. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1 . This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 13 -
K4B1G0446G K4B1G0846G
datasheet
tDVAC VIH.DIFF.AC.MIN Differential Input Voltage (i.e. DQS-DQS, CK-CK)
Rev. 1.01
DDR3 SDRAM
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
VIH.DIFF.MIN
0.0 half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX tDVAC time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ] Differential AC & DC Input Levels Symbol VIHdiff VILdiff VIHdiff(AC) VILdiff(AC) Parameter differential input high differential input low differential input high ac differential input low ac DDR3-800/1066/1333/1600/1866 min +0.2 NOTE 3 2 x (VIH(AC) - VREF) NOTE 3 max NOTE 3 -0.2 NOTE 3 2 x (VIL(AC) - VREF) unit V V V V NOTE 1 1 2 2
NOTE : 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max tDVAC [ps] @ |VIH/Ldiff(AC)| = 270mV min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD max tDVAC [ps] @ |VIH/Ldiff(AC)| = 250mV min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD max -
- 14 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH(AC) / VIL(AC)} for ADD/CMD signals] in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax [approximately the ac-levels { VIH(AC) / VIL(AC)} for DQ signals] in every half-cycle proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSEL time
Figure 3. Single-ended requirement for differential signals
VSS or VSSQ
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
[ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU Symbol VSEH VSEL Parameter Single-ended high-level for strobes Single-ended high-level for CK, CK Single-ended low-level for strobes Single-ended low-level for CK, CK DDR3-1066/1333/1600/1866 Min (VDD/2)+0.175 (VDD/2)+0.175 NOTE3 NOTE3 Max NOTE3 NOTE3 (VDD/2)-0.175 (VDD/2)-0.175 Unit V V V V NOTE 1, 2 1, 2 1, 2 1, 2
NOTE : 1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
- 15 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS Figure 4. VIX Definition [ Table 12 ] Cross point voltage for differential input signals (CK, DQS) Symbol VIX VIX Parameter Differential Input Cross Point Voltage relative to VDD/2 for CK,CK Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS DDR3-800/1066/1333/1600/1866 Min -150 -175 -150 Max 150 175 150 Unit mV mV mV 1 NOTE
NOTE : 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to Table 11 on page 15 for VSEL and VSEH standard values. 2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following. (VDD/2) + VIX(Min) - VSEL 25mV VSEH - ((VDD/2) + VIX(Max)) 25mV
8.5 Slew rate definition for Differential Input Signals
See 14.3 "Address/Command Setup, Hold and Derating :" on page 48 for single-ended slew rate definitions for address and command signals. See 14.4 "Data Setup, Hold and Slew Rate Derating :" on page 54 for single-ended slew rate definitions for data signals.
8.6 Slew rate definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5. [ Table 13 ] Differential input slew rate definition Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Measured From VILdiffmax VIHdiffmin To VIHdiffmin VILdiffmax Defined by VIHdiffmin - VILdiffmax Delta TRdiff VIHdiffmin - VILdiffmax Delta TFdiff
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
VIHdiffmin
0 VILdiffmax
delta TFdiff
delta TRdiff
Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK
- 16 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
9. AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 14 ] Single-ended AC & DC output levels Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) DDR3-800/1066/1333/1600/1866 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Units V V V V V 1 1 NOTE
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT=VDDQ/2.
9.2 Differential AC & DC Output Levels
[ Table 15 ] Differential AC & DC output levels Symbol VOHdiff(AC) VOLdiff(AC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800/1066/1333/1600/1866 +0.2 x VDDQ -0.2 x VDDQ Units V V NOTE 1 1
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT=VDDQ/2 at each of the differential outputs.
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and Figure 6. [ Table 16 ] Single-ended output slew rate definition Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC) Defined by VOH(AC)-VOL(AC) Delta TRse VOH(AC)-VOL(AC) Delta TFse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single-ended output slew rate Parameter Single ended output slew rate Symbol SRQse DDR3-800 Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 DDR3-1600 Min 2.5 Max 5 DDR3-1866 Min 2.5 Max 51) Units V/ns
Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) se : Single-ended Signals For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. - Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low). - Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies. VOH(AC)
VTT VOL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
- 17 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC)
for differential signals as shown in Table 18 and Figure 7.
[ Table 18 ] Differential output slew rate definition Description Differential output slew rate for rising edge Differential output slew rate for falling edge Measured From VOLdiff(AC) VOHdiff(AC) To VOHdiff(AC) VOLdiff(AC) Defined by VOHdiff(AC)-VOLdiff(AC) Delta TRdiff VOHdiff(AC)-VOLdiff(AC) Delta TFdiff
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 19 ] Differential output slew rate Parameter Differential output slew rate Symbol SRQdiff DDR3-800 Min 5 Max 10 DDR3-1066 Min 5 Max 10 DDR3-1333 Min 5 Max 10 DDR3-1600 Min 5 Max 10 DDR3-1866 Min 5 Max 12 Units V/ns
Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Differential Signals For Ron = RZQ/7 setting
VOHdiff(AC)
VTT VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 7. Differential Output Slew Rate Definition
9.5 Reference Load for AC Timing and Output Slew Rate
Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK/CK
DUT
DQ DQS DQS
VTT = VDDQ/2 25
Reference Point Figure 8. Reference Load for AC Timing and Output Slew Rate
- 18 -
K4B1G0446G K4B1G0846G
datasheet
Specification DDR3-800 0.4V 0.4V 0.67V-ns 0.67V-ns DDR3-1066 0.4V 0.4V 0.5V-ns 0.5V-ns DDR3-1333 0.4V 0.4V 0.4V-ns 0.4V-ns
Rev. 1.01
DDR3 SDRAM
9.6 Overshoot/Undershoot Specification
9.6.1 Address and Control Overshoot and Undershoot specifications
[ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 9) Maximum peak amplitude allowed for undershoot area (See Figure 9) Maximum overshoot area above VDD (See Figure 9) Maximum undershoot area below VSS (See Figure 9) Unit V V V-ns V-ns
DDR3-1600 0.4V 0.4V 0.33V-ns 0.33V-ns
DDR3-1866 0.4V 0.4V 0.28V-ns 0.28V-ns
Maximum Amplitude
Overshoot Area
Volts (V)
VDD VSS
Maximum Amplitude Time (ns)
Undershoot Area
Figure 9. Address and Control Overshoot and Undershoot Definition
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
[ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 10) Maximum peak amplitude allowed for undershoot area (See Figure 10) Maximum overshoot area above VDDQ (See Figure 10) Maximum undershoot area below VSSQ (See Figure 10) Specification DDR3-800 0.4V 0.4V 0.25V-ns 0.25V-ns DDR3-1066 0.4V 0.4V 0.19V-ns 0.19V-ns DDR3-1333 0.4V 0.4V 0.15V-ns 0.15V-ns DDR3-1600 0.4V 0.4V 0.13V-ns 0.13V-ns DDR3-1866 0.4V 0.4V 0.11V-ns 0.11V-ns Unit V V V-ns V-ns
Maximum Amplitude
Overshoot Area
Volts (V)
VDDQ VSSQ
Maximum Amplitude Time (ns)
Undershoot Area
Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
- 19 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
9.7 34ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows: RON34 = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm) The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows RONpu = VDDQ-VOUT l Iout l VOUT l Iout l under the condition that RONpu is turned off under the condition that RONpd is turned off
RONpd =
Output Driver VDDQ Ipu
To other circuity
RON
Pu
DQ RON Ipd Iout Vout VSSQ
Pd
Figure 11. Output Driver : Definition of Voltages and Currents
[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ; entire operating temperature range ; after proper ZQ calibration RONnom Resistor Vout VOLdc = 0.2 x VDDQ RON34pd 34Ohms RON34pu VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ RON40pd 40Ohms RON40pu VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ Mismatch between Pull-up and Pull-down, MMpupd VOMdc = 0.5 x VDDQ Min 0.6 0.9 0.9 0.9 0.9 0.6 0.6 0.9 0.9 0.9 0.9 0.6 -10 Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 1.1 1.1 1.4 1.4 1.1 1.1 1.1 1.1 1.4 1.4 1.1 1.1 10 % RZQ/6 RZQ/7 Units NOTE 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,4
NOTE : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ 4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ: MMpupd = RONpu - RONpd RONnom x 100
- 20 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
9.7.1 Output Drive Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 23 and Table 24. T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ *dRONdT and dRONdV are not subject to production test but are verified by design and characterization [ Table 23 ] Output Driver Sensitivity Definition Min RONPU@VOHDC RON@VOMDC RONPD@VOLDC 0.6 - dRONdTH * |T| - dRONdVH * |V| 0.9 - dRONdTM * |T| - dRONdVM * |V| 0.6 - dRONdTL * |T| - dRONdVL * |V| Max 1.1 + dRONdTH * |T| + dRONdVH * |V| 1.1 + dRONdTM * |T| + dRONdVM * |V| 1.1 + dRONdTL * |T| + dRONdVL * |V| Units RZQ/7 RZQ/7 RZQ/7
[ Table 24 ] Output Driver Voltage and Temperature Sensitivity Speed Bin dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH 0 0 0 0 0 0 DDR3-800/1066/1333 Min Max 1.5 0.15 1.5 0.15 1.5 0.15 Min 0 0 0 0 0 0 DDR3-1600/1866 Max 1.5 0.13 1.5 0.13 1.5 0.13 Units
%/C
%/mV
%/C
%/mV
%/C
%/mV
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register. ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as follows : VDDQ-VOUT l Iout l VOUT l Iout l under the condition that RTTpu is turned off
RTTpu =
under the condition that RTTpd is turned off
RTTpd =
Chip in Termination Mode ODT VDDQ Ipu
To other circuitry like RCV, ...
Iout=Ipd-Ipu
Pu
RTT
DQ RTT Ipd Iout
Pd
VOUT VSSQ
Figure 12. On-Die Termination : Definition of Voltages and Currents
- 21 -
K4B1G0446G K4B1G0846G
9.8.1 ODT DC Electrical Characteristics
datasheet
Rev. 1.01
DDR3 SDRAM
Table 25 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80, RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines: [ Table 25 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration MR1 (A9,A6,A2) RTT RESISTOR Vout VOL(DC) 0.2XVDDQ RTT120pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (0,1,0) 120 ohm RTT120pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT120 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT60pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (0,0,1) 60 ohm RTT60pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT60 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT40pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (0,1,1) 40 ohm RTT40pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT40 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT60pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (1,0,1) 30 ohm RTT60pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT60 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT60pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (1,0,0) 20 ohm RTT60pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT60 VIL(AC) to VIH(AC) Min 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 -5 Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 5 Unit RZQ RZQ RZQ RZQ RZQ RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 % NOTE 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,5,6
Deviation of VM w.r.t VDDQ/2, VM
- 22 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
NOTE : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2XVDDQ and 0.8XVDDQ. 4. Not a specification requirement, but a design guide line 5. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively
RTT
=
VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC))
6. Measurement definition for VM and VM : Measure voltage (VM) at test pin (midpoint) with no load
VM =
2 x VM VDDQ
-1
x 100
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ [ Table 26 ] ODT Sensitivity Definition Min RTT 0.9 - dRTTdT * |T| - dRTTdV * |V| Max 1.6 + dRTTdT * |T| + dRTTdV * |V| Units RZQ/2,4,6,8,12
[ Table 27 ] ODT Voltage and Temperature Sensitivity Min dRTTdT dRTTdV 0 0 Max 1.5 0.15 Units
%/C
%/mV
NOTE : These parameters may not be subject to production test. They are verified by design and characterization.
- 23 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.
VDDQ
CK,CK
DUT DQ, DM
DQS , DQS TDQS , TDQS
VTT= VSSQ RTT =25 ohm
VSSQ
Timing Reference Points
Figure 13. ODT Timing Reference Load
9.9.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided in Table 29. [ Table 28 ] ODT Timing Definitions Symbol tAON tAONPD tAOF tAOFPD tADC Begin Point Definition Rising edge of CK - CK defined by the end point of ODTLon Rising edge of CK - CK with ODT being first registered high Rising edge of CK - CK defined by the end point of ODTLoff Rising edge of CK - CK with ODT being first registered low Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4 of ODTLcwn8 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively Figure Figure 14 Figure 15 Figure 16 Figure 17 Figure 18
[ Table 29 ] Reference Settings for ODT Timing Measurements Measured Parameter tAON tAONPD tAOF tAOFPD tADC RTT_Nom Setting RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/12 RTT_Wr Setting NA NA NA NA NA NA NA NA RZQ/2 VSW1[V] 0.05 0.10 0.05 0.10 0.05 0.10 0.05 0.10 0.20 VSW2[V] 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30 NOTE
- 24 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
Begin point : Rising edge of CK - CK defined by the end point of ODTLon
CK VTT CK
tAON
TSW2
DQ, DM DQS , DQS TDQS , TDQS
TSW1 VSW2 VSW1
VSSQ
VSSQ
End point Extrapolated point at VSSQ Figure 14. Definition of tAON
Begin point : Rising edge of CK - CK with ODT being first registered high
CK VTT CK
tAONPD
TSW2
DQ, DM DQS , DQS TDQS , TDQS
TSW1 VSW2 VSW1
VSSQ
VSSQ
End point Extrapolated point at VSSQ Figure 15. Definition of tAONPD
Begin point : Rising edge of CK - CK defined by the end point of ODTLoff
CK VTT CK
tAOF
VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS
End point Extrapolated point at VRTT_Nom
TSW2
VSW2 VSW1
TSW1
VSSQ
TD_TAON_DEF
Figure 16. Definition of tAOF
- 25 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
Begin point : Rising edge of CK - CK with ODT being first registered low
CK VTT CK
tAOFPD
VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS
End point Extrapolated point at VRTT_Nom
TSW2
VSW2 VSW1
TSW1
VSSQ
Figure 17. Definition of tAOFPD
Begin point : Rising edge of CK - CK defined by the end point of ODTLcnw
Begin point : Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8
CK VTT CK
tADC tADC
VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS
End point Extrapolated point at VRTT_Nom VRTT_Nom
TSW21 End point Extrapolated point TSW11 at VRTT_Nom VSW1
VSW2
TSW22 TSW12
VRTT_Wr
End point Extrapolated point at VRTT_Wr
VSSQ
Figure 18. Definition of tADC
- 26 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
10. IDD Current Measure Method
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and IDDQ measurements. - IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. - IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply : - "0" and "LOW" is defined as VIN <= VILAC(max). - "1" and "HIGH" is defined as VIN >= VIHAC(min). - "FLOATING" is defined as inputs are VREF = VDD / 2. - "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 30 - "Basic IDD and IDDQ Measurement Conditions" are described in Table 31 - Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39. - IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 - Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. - Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW} - Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH} - RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms; During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC
[ Table 30 ] Timing used for IDD and IDDQ Measured - Loop Patterns Parameter tCKmin(IDD) CL(IDD) tRCDmin(IDD) tRCmin(IDD) tRASmin(IDD) tRPmin(IDD) tFAW(IDD) tRRD(IDD) x4/x8 x16 x4/x8 x16 Bin DDR3-800 6-6-6 2.5 6 6 21 15 6 16 20 4 4 36 44 64 120 140 DDR3-1066 7-7-7 1.875 7 7 27 20 7 20 27 4 6 48 59 86 160 187 DDR3-1333 9-9-9 1.5 9 9 33 24 9 20 30 4 5 60 74 107 200 234 DDR3-1600 11-11-11 1.25 11 11 39 28 11 24 32 5 6 72 88 128 240 280 DDR3-1866 13-13-13 1.07 13 13 45 32 13 26 33 5 6 85 103 150 281 328 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
tRFC(IDD) - 512Mb tRFC(IDD) - 1Gb tRFC(IDD) - 2Gb tRFC(IDD) - 4Gb tRFC(IDD) - 8Gb
- 27 -
K4B1G0446G K4B1G0846G
datasheet
IDD IDDQ
Rev. 1.01
DDR3 SDRAM
VDD
RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ
VDDQ
DQS, DQS DQ, DM, TDQS, TDQS
RTT = 25 Ohm VDDQ/2
VSS
VSSQ
[NOTE : DIMM level Output test load condition may be different from above]
Figure 19. Measurement Setup and Test Load for IDD and IDDQ Measurements
Application specific memory channel environment
IDDQ Test Load
Channel IO Power Simulation
IDDQ Simulation
IDDQ Measurement
Correlation
Correction
Channel IO Power Number
Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.
- 28 -
K4B1G0446G K4B1G0846G
datasheet
Description
Rev. 1.01
DDR3 SDRAM
[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
Symbol Operating One Bank Active-Precharge Current IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 32 Operating One Bank Active-Read-Precharge Current IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 33 Precharge Standby Current IDD2N CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34 Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35 IDDQ2NT Precharge Standby ODT IDDQ Current Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge Power-Down Current Slow Exit IDD2P0 CKE: Low; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exi3) Precharge Power-Down Current Fast Exit IDD2P1 CKE: Low; External clock: On; tCK, CL: see Table 30 on page 27; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0 Active Standby Current IDD3N CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34 Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0 Operating Burst Read Current IDD4R CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 12); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 36 IDDQ4R Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Operating Burst Write Current IDD4W CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: see Table 37 Burst Refresh Current IDD5B CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 38 Self Refresh Current: Normal Temperature Range IDD6 TCASE: 0 - 85C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: SelfRefresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
- 29 -
K4B1G0446G K4B1G0846G
datasheet
Description
Rev. 1.01
DDR3 SDRAM
[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
Symbol Operating Bank Interleave Read Current IDD7 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 on page 27 ; BL: 81); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 39 IDD8 RESET Low Current RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal : FLOATING
NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B 2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range 6) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
- 30 -
K4B1G0446G K4B1G0846G
[ Table 32 ] IDD0 Measurement - Loop Pattern1) Command Sub-Loop
datasheet
A[15:11] Cycle Number BA[2:0] A[9:7] A[10] RAS CAS ODT WE CS
Rev. 1.01
DDR3 SDRAM
Data2) A[6:3] A[2:0] 0 0 0 0 0 0 0 0
CK/CK
CKE
0
0 1,2 3,4 ... nRAS ... 1*nRC + 0 1*nRC + 1, 2
ACT D, D D, D PRE ACT D, D D, D PRE
0 1 1 0 0 1 1 0
0 0 1 0 0 0 1 0
1 0 1 1 1 0 1 1
1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 F F F F
repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC + 3, 4 ... 1*nRC + nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
NOTE : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL.
- 31 -
K4B1G0446G K4B1G0846G
[ Table 33 ] IDD1 Measurement - Loop Pattern1) Command Sub-Loop
datasheet
A[15:11] Cycle Number BA[2:0] A[9:7] A[6:3] A[10] RAS CAS ODT WE CS
Rev. 1.01
DDR3 SDRAM
Data2) 00000000 00110011 Data2) A[2:0] 0 0 0 0 0 0 0 0 0 0 A[2:0] 0 0 0 0
CK/CK
CKE
0
0 1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC + 1, 2
ACT D, D D, D RD PRE ACT D, D D, D RD PRE
0 1 1 0 0 0 1 1 0 0
0 0 1 1 0 0 0 1 1 0
1 0 1 0 1 1 0 1 0 1
1 0 1 1 0 1 0 1 1 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
00 00 00 00 00 00 00 00 00 00
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 F F F F F
repeat pattern 1...4 until nRCD- 1, truncate if necessary repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC + 3, 4 ... 1*nRC + nRCD ... 1*nRC + nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 34 ] IDD2 and IDD3N Measurement - Loop Pattern1) Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK A[9:7] 0 0 0 0 A[6:3] 0 0 F F A[10] 0 0 0 0 CKE RAS CAS ODT 0 0 0 0 WE 0 0 1 1
0
0 1 2 3
D D D D
CS 1 1 1 1
0 0 1 1
0 0 1 1
0 0 0 0
00 00 00 00
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-27 28-31
repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
NOTE : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL.
- 32 -
K4B1G0446G K4B1G0846G
datasheet
Command A[15:11] Cycle Number BA[2:0] A[9:7] A[6:3] A[10] RAS CAS ODT WE CS
Rev. 1.01
DDR3 SDRAM
Data2) 00000000 00110011 Data2) A[2:0] 0 0 0 0 A[2:0] 0 0 0 0 0 0
[ Table 35 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern1) Sub-Loop 0 CK/CK CKE
0 1 2 3
D D D D
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
00 00 00 00
0 0 0 0
0 0 0 0
0 0 F F
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-27 28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
NOTE : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL.
[ Table 36 ] IDD4R and IDDQ4R Measurement - Loop Pattern1) Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK A[9:7] 0 0 0 0 0 0 A[6:3] 0 0 0 F F F A[10] 0 0 0 0 0 0 ODT 0 0 0 0 0 0 CKE RAS CAS 0 0 1 0 0 1 WE 1 0 1 1 0 1
0
0 1 2,3 4 5
RD D D,D RD D D,D
CS 0 1 1 0 1 1
1 0 1 1 0 1
0 0 0 0 0 0
00 00 00 00 00 00
Static High
toggling
6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
- 33 -
K4B1G0446G K4B1G0846G
[ Table 37 ] IDD4W Measurement - Loop Pattern1) Command Sub-Loop
datasheet
A[15:11] Cycle Number BA[2:0] A[9:7] A[6:3] A[10] RAS CAS ODT WE CS
Rev. 1.01
DDR3 SDRAM
Data2) 00000000 00110011 Data2) A[2:0] 0 0 0 0 0 0 A[2:0] 0 0 0
CK/CK
CKE
0
0 1 2,3 4 5
WR D D,D WR D D,D
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
0 0 1 0 0 1
1 1 1 1 1 1
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
Static High
toggling
6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 38 ] IDD5B Measurement - Loop Pattern1) Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK A[9:7] 0 0 0 A[6:3] 0 0 F A[10] 0 0 0 ODT 0 0 0 CKE RAS CAS 0 0 1 WE 1 0 1
0 1
0 1,2 3,4 5...8
REF D D,D
CS 0 1 1
0 0 1
0 0 0
00 00 00
repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Static High
toggling
9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC - 1
NOTE : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL.
- 34 -
K4B1G0446G K4B1G0846G
[ Table 39 ] IDD7 Measurement - Loop Pattern1) Command Sub-Loop
datasheet
A[15:11] Cycle Number BA[2:0] A[9:7] A[6:3] A[10] RAS CAS ODT WE CS
Rev. 1.01
DDR3 SDRAM
Data2) 00000000 00110011 00110011 00000000 A[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CK/CK
CKE
0 0 1 2 ... nRRD 1 nRRD + 1 nRRD + 2 ... 2 3 4 5 6 7 8 Static High toggling 9 2 * nRRD 3 * nRRD 4 * nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 10 2*nFAW+1 2*nFAW+2 2*nFAW+nRRD 11 2*nFAW+nRRD+1 2*nFAW+nRRD+2 12 13 14 15 16 17 18 19 2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD
ACT RDA D ACT RDA D
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0
0 0 0 0 0 0
0 0 0 1 1 1
00 00 00 00 00 00
0 1 0 0 1 0
0 0 0 0 0 0
0 0 0 F F F
repeat above D Command until nRRD - 1
repeat above D Command until 2*nRRD-1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 1, but BA[2:0] = 7 D ACT RDA D ACT RDA D 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 7 0 0 0 1 1 1 00 00 00 00 00 00 00 0 0 1 0 0 1 0 0 0 0 0 0 0 0 F F F F 0 0 0 Assert and repeat above D Command until 2*nFAW - 1, if necessary
Repeat above D Command until 2*nFAW + nRRD - 1
Repeat above D Command until 2*nFAW + 2*nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 Assert and repeat above D Command until 3*nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 Assert and repeat above D Command until 4*nFAW - 1, if necessary
NOTE : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.
- 35 -
K4B1G0446G K4B1G0846G
datasheet
256Mx4 (K4B1G0446G) DDR3-1066 7-7-7 35 40 10 12 15 20 40 15 15 20 55 35 60 85 10 100 10 DDR3-1333 9-9-9 35 42 10 12 15 25 40 15 15 20 65 35 70 90 10 125 10 DDR3-1600 11-11-11 35 45 10 12 15 25 40 15 15 20 75 35 80 90 10 128 10
Rev. 1.01
DDR3 SDRAM
11. 1Gb DDR3 SDRAM G-die IDD Specification Table
[ Table 40 ] IDD Specification for 1Gb DDR3 G-die Symbol IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2NT IDDQ2NT IDD2Q IDD3P IDD3N IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD7 IDD8 DDR3-1866 13-13-13 40 50 10 12 20 25 40 20 15 20 85 35 90 105 10 135 10 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit NOTE
128Mx8 (K4B1G0846G) Symbol IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2NT IDDQ2NT IDD2Q IDD3P IDD3N IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD7 IDD8 DDR3-1066 7-7-7 35 40 10 12 15 20 70 15 15 20 60 50 60 85 10 105 10 DDR3-1333 9-9-9 35 42 10 12 15 25 70 15 15 20 70 50 70 90 10 130 10 DDR3-1600 11-11-11 35 48 10 12 15 25 70 15 15 20 80 50 80 90 10 135 10 DDR3-1866 13-13-13 40 50 10 12 20 25 70 20 15 20 90 50 95 105 10 140 10 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit NOTE
- 36 -
K4B1G0446G K4B1G0846G
datasheet
Symbol CIO CCK CDCK CI CDDQS CDI_CTRL CDI_ADD_CMD CDIO CZQ DDR3-800 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.2 0.3 0.5 0.3 3 DDR3-1066 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 2.7 1.6 0.15 1.5 0.2 0.3 0.5 0.3 3 DDR3-1333 Min 1.5 0.8 0 0.75 0 -0.4 -0.4 -0.5 Max 2.5 1.4 0.15 1.3 0.15 0.2 0.4 0.3 3 DDR3-1600 Min 1.5 0.8 0 0.75 0 -0.4 -0.4 -0.5 Max 2.3 1.4 0.15 1.3 0.15 0.2 0.4 0.3 3
Rev. 1.01
DDR3 SDRAM
12. Input/Output Capacitance
[ Table 41 ] Input/Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance delta (CK and CK) Input capacitance (All other input-only pins) Input capacitance delta (DQS and DQS) Input capacitance delta (All control input-only pins) Input capacitance delta (all ADD and CMD input-only pins) Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS) Input/output capacitance of ZQ pin DDR3-1866 Min 1.4 0.8 0 0.75 0 -0.4 -0.4 -0.5 Max 2.2 1.3 0.15 1.2 0.15 0.2 0.4 0.3 3 Units pF pF pF pF pF pF pF pF pF NOTE 1,2,3 2,3 2,3,4 2,3,6 2,3,5 2,3,7,8 2,3,9,10 2,3,11 2, 3, 12
NOTE : 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK 5. Absolute value of CIO(DQS)-CIO(DQS) 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTRL applies to ODT, CS and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance on ZQ pin: 5pF
- 37 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866
13.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device.
13.1.1 Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. N
j=1
tCKj
N
N=200
13.1.2 Definition for tCK(abs)
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test.
13.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: N
j=1
tCHj
N x tCK(avg)
N=200
j=1
N
tCLj
N x tCK(avg)
N=200
13.1.4 Definition for note for tJIT(per), tJIT(per, Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for tJIT(cc), tJIT(cc, Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi} tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
- 38 -
K4B1G0446G K4B1G0846G
datasheet
Symbol tRFC tREFI 0 C TCASE 85C 85 C < TCASE 95C 1Gb 110 7.8 3.9 2Gb 160 7.8 3.9 4Gb 300 7.8 3.9
Rev. 1.01
DDR3 SDRAM
13.2 Refresh Parameters by Device Density
[ Table 42 ] Refresh parameters by device density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval 8Gb 350 7.8 3.9 Units ns s s 1 NOTE
NOTE : 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material.
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. [ Table 43 ] DDR3-800 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 Supported CL Settings Supported CWL Settings CWL = 5 CWL = 5 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) min 15 15 15 52.5 37.5 3.0 2.5 5,6 5 DDR3-800 6-6-6 max 20 9*tREFI 3.3 3.3 ns ns ns ns ns ns ns nCK nCK 1,2,3,4,10,11 1,2,3 Units NOTE
[ Table 44 ] DR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6 CL = 6 CL = 7 CL = 8 Supported CL Settings Supported CWL Settings CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.875 5,6,7,8 5,6 1.875 Reserved <2.5 2.5 Reserved Reserved <2.5 min 13.125 13.125 13.125 50.625 37.5 3.0 Reserved 3.3 DDR3-1066 7-7-7 max 20 9*tREFI 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 1,2,3,4,5,10, 11 4 1,2,3,5 1,2,3,4 4 1,2,3,4,9 4 1,2,3 Units NOTE
- 39 -
K4B1G0446G K4B1G0846G
[ Table 45 ] DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6,7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CL = 10 Supported CL Settings Supported CWL Settings CWL = 5,6 CWL = 7 CWL = 5,6 CWL = 7
datasheet
DDR3-1333 9 -9 - 9 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.5 5,6,7,8,9 5,6,7 1.5 Reserved <1.875 1.875 Reserved Reserved <1.875 1.875 Reserved Reserved <2.5 2.5 Reserved Reserved Reserved <2.5 min 13.5 (13.125)9 13.5 (13.125)9 13.5 (13.125)9 49.5 (49.125)9 36 3.0 Reserved 3.3 max 20 9*tREFI 3.3
Rev. 1.01
DDR3 SDRAM
Units
NOTE
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 1,2,3,4,6,10, 11 4 1,2,3,6 1,2,3,4,6 4 4 1,2,3,4,6 1,2,3,4 4 1,2,3,6 1,2,3,4 4 1,2,3,4,9 4 1,2,3
- 40 -
K4B1G0446G K4B1G0846G
[ Table 46 ] DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6,7,8 CWL = 5 CL = 6 CWL = 6 CWL = 7, 8 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 8 CWL = 5 CL = 8 CWL = 6 CWL = 7 CWL = 8 CWL = 5,6 CL = 9 CWL = 7 CWL = 8 CWL = 5,6 CL = 10 CWL = 7 CWL = 8 CL = 11 Supported CL Settings Supported CWL Settings CWL = 5,6,7 CWL = 8
datasheet
DDR3-1600 11-11-11 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.25 5,6,7,8,9,10,11 5,6,7,8 1.5 Reserved Reserved <1.5 1.5 Reserved Reserved <1.875 1.875 Reserved Reserved Reserved <1.875 1.875 Reserved Reserved Reserved <2.5 2.5 Reserved Reserved Reserved <2.5 min 13.75 (13.125)9 13.75 (13.125)9 13.75 (13.125)9 48.75 (48.125)9 35 3.0 Reserved 3.3 max 20 9*tREFI 3.3
Rev. 1.01
DDR3 SDRAM
Units
NOTE
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 1,2,3,4,7,10, 11 4 1,2,3,7 1,2,3,4,7 4 4 1,2,3,4,7 1,2,3,4,7 4 4 1,2,3,7 1,2,3,4,7 1,2,3,4 4 1,2,3,4,7 1,2,3,4 4 1,2,3,7 1,2,3,4 4 1,2,3,9
- 41 -
K4B1G0446G K4B1G0846G
[ Table 47 ] DDR3-1866 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6,7,8,9 CWL = 5 CL = 6 CWL = 6 CWL = 7,8,9 CWL = 5 CL = 7 CWL = 6 CWL = 7,8,9 CWL = 5 CL = 8 CWL = 6 CWL = 7 CWL = 8,9 CWL = 5,6 CL = 9 CWL = 7 CWL = 8 CWL = 9 CWL = 5,6 CL = 10 CWL = 7 CWL = 8 CWL = 5,6,7 CL = 11 CWL = 8 CWL = 9 CL = 12 CL = 13 Supported CL Settings Supported CWL Settings CWL = 5,6,7,8 CWL = 9 CWL = 5,6,7,8 CWL = 9
datasheet
DDR3-1866 13-13-13 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.07 5,6,7,8,9,10,11,13 5,6,7,8,9 1.25 Reserved Reserved Reserved Reserved <1.25 1.5 Reserved Reserved 1.5 1.5 Reserved Reserved Reserved <1.875 1.875 Reserved Reserved Reserved 1.875 1.875 Reserved Reserved <2.5 2.5 Reserved Reserved Reserved 2.5 min 13.91 (13.125)12 13.91 (13.125)12 13.91 (13.125)12 47.91 (47.125)12 34 3.0 Reserved 3.3 max 20 9*tREFI 3.3
Rev. 1.01
DDR3 SDRAM
Units
NOTE
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 1,2,3,4,8,10, 11 4 1,2,3,8 1,2,3,4,8 4 4 1,2,3,4,8 4 4 1,2,3,8 1,2,3,4,8 4 4 1,2,3,4,8 4 4 4 1,2,3,8 1,2,3,4,8 4 1,2,3,4,8 1,2,3,4 4 1,2,3,4 4 1,2,3,9
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K4B1G0446G K4B1G0846G
13.3.1 Speed Bin Table Notes
datasheet
Rev. 1.01
DDR3 SDRAM
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
NOTE : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "Supported CL". 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED. 4. "Reserved" settings are not allowed. User must program a different value. 5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should program 13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accodingly. For example, 49.125ns, (tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for DDR31600. 10. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate. 11. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding. 12. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and tRPmin (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin = 34ns + 13.125ns)
- 43 -
K4B1G0446G K4B1G0846G
datasheet
Speed Parameter Symbol MIN DDR3-800 MAX DDR3-1066 MIN MAX MIN
Rev. 1.01
DDR3 SDRAM
14. Timing Parameters by Speed Grade
[ Table 48 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333
DDR3-1333 MAX Units NOTE
Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 ... 49, 50 cycles Absolute clock HIGH pulse width Absolute clock Low pulse width Data Timing DQS,DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to VIH(AC)VIL(AC) levels Data hold time to DQS, DQS referenced to VIH(AC)VIL(AC) levels DQ and DM Input pulse width for each input Data Strobe Timing DQS, DQS differential READ Preamble DQS, DQS differential READ Postamble DQS, DQS differential output high time DQS, DQS differential output low time DQS, DQS differential WRITE Preamble DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from rising CK, CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS,DQS falling edge setup time to CK, CK rising edge DQS,DQS falling edge hold time to CK, CK rising edge tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH 0.9 0.3 0.38 0.38 0.9 0.3 -400 -800 0.45 0.45 -0.25 0.2 0.2 NOTE 19 NOTE 11 400 400 400 0.55 0.55 0.25 0.9 0.3 0.38 0.38 0.9 0.3 -300 -600 0.45 0.45 -0.25 0.2 0.2 NOTE 19 NOTE 11 300 300 300 0.55 0.55 0.25 0.9 0.3 0.4 0.4 0.9 0.3 -255 -500 0.45 0.45 -0.25 0.2 0.2 NOTE 19 NOTE 11 255 250 250 0.55 0.55 0.25 tCK tCK tCK(avg) tCK(avg) tCK tCK ps ps ps tCK tCK tCK(avg) tCK(avg) tCK(avg) 13,f 13,14,f 12,13,14 29, 31 30, 31 c c, 32 c, 32 13, 19, g 11, 13, b 13, g 13, g tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) AC175 tDS(base) AC150 tDH(base) DC100 tDIPW 0.38 -800 75 125 150 600 200 400 400 0.38 -600 25 75 100 490 150 300 300 0.38 -500 30 65 400 125 250 250 ps tCK(avg) ps ps ps ps ps ps 13 13, g 13,14, f 13,14, f d, 17 d, 17 d, 17 28 tCK(DLL_OFF) tCK(avg) tCK(abs) tCH(avg) tCL(avg) tJIT(per) tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tCH(abs) tCL(abs) 0.43 0.43 - 147 - 175 - 194 - 209 - 222 - 232 - 241 - 249 - 257 - 263 - 269
tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max
8
-
8
-
8
-
ns ps
6
See Speed Bins Table
tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max
ps tCK(avg) tCK(avg) ps ps ps ps
0.47 0.47 -100 -90 200 180
0.53 0.53 100 90
0.47 0.47 -90 -80 180 160
0.53 0.53 90 80
0.47 0.47 -80 -70 160 140
0.53 0.53 80 70
147 175 194 209 222 232 241 249 257 263 269
- 132 - 157 - 175 - 188 - 200 - 209 - 217 - 224 - 231 - 237 - 242
132 157 175 188 200 209 217 224 231 237 242
- 118 - 140 - 155 - 168 - 177 - 186 - 193 - 200 - 205 - 210 - 215
118 140 155 168 177 186 193 200 205 210 215
ps ps ps ps ps ps ps ps ps ps ps ps 24 25 26
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max 0.43 0.43 0.43 0.43 -
tCK(avg) tCK(avg)
-
-
-
- 44 -
K4B1G0446G K4B1G0846G
datasheet
Speed Parameter Symbol MIN DDR3-800 MAX DDR3-1066 MIN MAX MIN tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW tIS(base) AC175 tIS(base) AC150 tIH(base) DC100 tIPW 1 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns) 4 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns) 4 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns) 4
Rev. 1.01
DDR3 SDRAM
DDR3-1333 MAX Units NOTE
[ Table 48 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)
Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS# to CAS# command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels Command and Address hold time from CK, CK referenced to VIH(AC) / VIL(AC) levels Control & Address Input pulse width for each input Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or PowerDown Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or PowerDown Exit (PDX) or Reset Exit tXS tXSDLL tCKESR tCKSRE tCKSRX max(5nCK,tRF C + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) max(5nCK,tRF C + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) max(5nCK,tRF C + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) nCK tXPR max(5nCK, tRFC + 10ns) max(5nCK, tRFC + 10ns) max(5nCK, tRFC + 10ns) tZQinitI tZQoper tZQCS 512 256 64 512 256 64 512 256 64 nCK nCK nCK 23 nCK nCK 1 nCK ns 22 e e e ns ns ps ps ps ps e e b,16 b,16,27 b,16 28 ns nCK nCK e e,18 e
WR + roundup (tRP / tCK(AVG)) 1 -
See "Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 42 max (4nCK,10ns) max (4nCK,10ns) 40 50 200 200 + 150 275 900 max (4nCK,7.5ns) max (4nCK,10ns) 37.5 50 125 125 + 150 200 780 max (4nCK,6ns) max (4nCK,7.5ns) 30 45 65 65+125 140 620 -
-
-
- 45 -
K4B1G0446G K4B1G0846G
datasheet
Speed Parameter Symbol MIN DDR3-800 MAX DDR3-1066 MIN MAX MIN max (3nCK, 7.5ns) max (10nCK, 24ns) max (3nCK, 7.5ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL+4+WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) max (3nCK, 7.5ns) max (10nCK, 24ns) max (3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL+4+WR+1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min)
Rev. 1.01
DDR3 SDRAM
DDR3-1333 MAX Units NOTE
[ Table 48 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)
Power Down Timing Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXP max (3nCK,6ns) max (10nCK, 24ns) max (3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL+4+WR+1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) -
tXPDLL
-
-
-
2
CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WR command to Power Down entry (BL4MRS) Timing of WRA command to Power Down entry (BL4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry ODT Timing ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8 Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed DQS/DQS delay after tDQS margining mode is programmed Write leveling setup time from rising CK, CK crossing to rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS crossing to rising CK, CK crossing Write leveling output delay Write leveling output error
tCKE tCPDED tPD tACTPDEN tPRPDEN tRDPDEN tWRPDEN
9*tREFI -
9*tREFI -
9*tREFI nCK 9 nCK tCK nCK nCK 15 20 20
tWRAPDEN
-
-
-
nCK
10
tWRPDEN
-
-
-
nCK
9
tWRAPDEN tREFPDEN tMRSPDEN
-
-
-
nCK
10 20,21
ODTH4 ODTH8 tAONPD tAOFPD tAON tAOF tADC
4 6 2 2 -400 0.3 0.3
8.5 8.5 400 0.7 0.7
4 6 2 2 -300 0.3 0.3
8.5 8.5 300 0.7 0.7
4 6 2 2 -250 0.3 0.3
8.5 8.5 250 0.7 0.7
nCK nCK ns ns ps tCK(avg) tCK(avg) 7,f 8,f f
tWLMRD tWLDQSEN tWLS tWLH tWLO tWLOE
40 25 325 325 0 0
9 2
40 25 245 245 0 0
9 2
40 25 195 195 0 0
9 2
tCK tCK ps ps ns ns
3 3
- 46 -
K4B1G0446G K4B1G0846G
datasheet
Speed Parameter Symbol MIN DDR3-1600 MAX MIN DDR3-1866 tCK(DLL_OFF) tCK(avg) tCK(abs) tCH(avg) tCL(avg) tJIT(per) tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tCH(abs) tCL(abs) 0.43 0.43 -103 -122 -136 -147 -155 -163 -169 -175 -180 -184 -188
tCK(avg)min + tJIT(per)min
Rev. 1.01
DDR3 SDRAM
MAX Units NOTE
[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866
Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 ... 49, 50 cycles Absolute clock HIGH pulse width Absolute clock Low pulse width Data Timing DQS,DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to VIH(AC)VIL(AC) levels tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) AC150 tDS(base) AC135 tDH(base) DC100 tDIPW 0.38 -450 10 45 360 100 225 225 0.38 -390 0 20 320 85 195 195 ps tCK(avg) ps ps ps ps ps ps 13 13, g 13,14, f 13,14, f d, 17 d, 17 d, 17 28 8 8 See Speed Bins Table
tCK(avg)max + tJIT(per)max tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max
-
ns ps ps tCK(avg) tCK(avg) ps ps ps ps
6
0.47 0.47 -70 -60 140 120
0.53 0.53 70 60
0.47 0.47 -60 -50 120 100
0.53 0.53 60 50
103 122 136 147 155 163 169 175 180 184 188
-88 -105 -117 -126 -133 -139 -145 -150 -154 -158 -161
88 105 117 126 133 139 145 150 154 158 161
ps ps ps ps ps ps ps ps ps ps ps ps 24 25 26
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max 0.43 0.43 -
tCK(avg) tCK(avg)
-
Data hold time to DQS, DQS referenced to VIH(AC)VIL(AC) levels DQ and DM Input pulse width for each input Data Strobe Timing DQS, DQS differential READ Preamble DQS, DQS differential READ Postamble DQS, DQS differential output high time DQS, DQS differential output low time DQS, DQS differential WRITE Preamble DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from rising CK, CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS,DQS falling edge setup time to CK, CK rising edge DQS,DQS falling edge hold time to CK, CK rising edge
-
tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH
0.9 0.3 0.4 0.4 0.9 0.3 -225 -450 0.45 0.45 -0.27 0.9 0.3
NOTE 19 NOTE 11 225 225 225 0.55 0.55 0.27 NOTE 19 NOTE 11
0.9 0.3 0.4 0.4 0.9 0.3 -195 -390 0.45 0.45 -0.27 0.18 0.18
NOTE 19 NOTE 11 195 195 195 0.55 0.55 0.27 -
tCK tCK tCK(avg) tCK(avg) tCK tCK ps ps ps tCK tCK tCK(avg) tCK(avg) tCK(avg)
13, 19, g 11, 13, b 13, g 13, g
13,f 13,14,f 12,13,14 29, 31 30, 31 c c, 32 c, 32
- 47 -
K4B1G0446G K4B1G0846G
datasheet
Speed Parameter Symbol MIN DDR3-1600 MAX MIN DDR3-1866 tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW tIS(base) AC175 1 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns) 4 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns) 4 WR + roundup (tRP / tCK(AVG)) 1
Rev. 1.01
DDR3 SDRAM
Units NOTE
[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)
MAX
Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS# to CAS# command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size nCK nCK nCK ns 22 e e e ns ns ps ps ps ps ps ps e e b,16 b,16 b,16 b,16,27 b,16 28 ns nCK nCK e e,18 e
See "Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 42 max (4nCK,6ns) max (4nCK,7.5ns) 30 40 45 170 120 560 max (4nCK, 5ns) max (4nCK, 6ns) 27 35 65 150 100 535 -
-
Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels
tIS(base) AC150 tIS(base) AC135 tIS(base) AC125
Command and Address hold time from CK, CK referenced to VIH(AC) / VIL(AC) levels Control & Address Input pulse width for each input Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or PowerDown Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or PowerDown Exit (PDX) or Reset Exit
tIH(base) DC100 tIPW
tZQinitI tZQoper tZQCS
512 256 64
-
max(512nCK,640ns) max(256nCK,320ns) max(64nCK,80ns)
-
nCK nCK nCK 23
tXPR
max(5nCK, tRFC + 10ns)
-
max(5nCK, tRFC + 10ns)
-
tXS tXSDLL tCKESR tCKSRE tCKSRX
max(5nCK,tRFC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns)
-
max(5nCK,tRFC + 10ns) tDLLK(min) tCKE(min) + 1nCK max(5nCK, 10ns) max(5nCK, 10ns)
nCK
- 48 -
K4B1G0446G K4B1G0846G
datasheet
Speed Parameter Symbol MIN DDR3-1600 MAX MIN DDR3-1866
Rev. 1.01
DDR3 SDRAM
Units NOTE
[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)
MAX
Power Down Timing Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WR command to Power Down entry (BL4MRS) Timing of WRA command to Power Down entry (BL4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry ODT Timing ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8 Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed DQS/DQS delay after tDQS margining mode is programmed Write leveling setup time from rising CK, CK crossing to rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS crossing to rising CK, CK crossing Write leveling output delay Write leveling output error tWLMRD tWLDQSEN tWLS tWLH tWLO tWLOE 40 25 165 165 0 0 7.5 2 40 25 140 140 0 0 7.5 2 tCK tCK ps ps ns ns 3 3 ODTH4 ODTH8 tAONPD tAOFPD tAON tAOF tADC 4 6 2 2 -225 0.3 0.3 8.5 8.5 225 0.7 0.7 4 6 2 2 -195 0.3 0.3 8.5 8.5 195 0.7 0.7 nCK nCK ns ns ps tCK(avg) tCK(avg) 7,f 8,f f tXP max (3nCK,6ns) max (10nCK, 24ns) max (3nCK,5ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL + 4 +WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) max(3nCK,6ns) -
tXPDLL
-
max(10nCK,24ns)
-
2
tCKE tCPDED tPD tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN tREFPDEN tMRSPDEN
9*tREFI -
max(3nCK,5ns) 2 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL + 4 +WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min)
9*tREFI nCK nCK nCK nCK 9 10 9 10 20,21 nCK tCK nCK nCK 15 20 20
- 49 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
14.1 Jitter Notes
Specific Note a Unit 'tCK(avg)' represents the actual tCK(avg) of the input clock under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U), DQS(L/U)) crossing. For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/ max usage!)
Specific Note b
Specific Note c
Specific Note d
Specific Note e
Specific Note f
Specific Note g
- 50 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
14.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register 5. Value must be rounded-up to next higher integer value 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet" 8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet". 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles as programmed in MR0 11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing Diagram Datasheet. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD 13. Value is only valid for RON34 14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method. 15. tREFI depends on TOPER 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC). See "Address/Command Setup, Hold and Derating :" on page 52. . 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC). See "Data Setup, Hold and Slew Rate Derating :" on page 59. 18. Start of internal write transaction is defined as follows ; For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL 19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Datasheet" 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet". 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the 'Output Driver Voltage and Temperature Sensitivity' and 'ODT Voltage and Temperature Sensitivity' tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection (TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:
0.5 (1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
= 0.133 ~ 128ms ~
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR31333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv - 150 mV) / 1 V/ns]. 28. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC) 29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge. 30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge. 31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application. 32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application. 33. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 to accommodate for the lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mv - 125mV) / 1 V/ns].
- 51 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table 50) to the tIS and tIH derating value (see Table 51) respectively. Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(DC) to ac region', use nominal slew rate for derating value (see Figure 21). If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 23). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded 'dc to VREF(DC) region', use nominal slew rate for derating value (see Figure 22). If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 24). For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 55). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
[ Table 50 ] ADD/CMD Setup and Hold Base-Values for 1V/ns [ps] tIS(base) AC175 tIS(base) AC150 tIS(base)-AC135 tIS(base)-AC125 tIH(base)-DC100 DDR3-800 200 350 275 DDR3-1066 125 275 200 DDR3-1333 65 190 140 DDR3-1600 45 170 120 DDR3-1866 65 150 100 reference VIH/L(AC) VIH/L(AC) VIH/L(AC) VIH/L(AC) VIH/L(DC)
NOTE : 1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-Ck slew rate 2. The tIS(base)-AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125ps for DDR3-800/1066 or 100ps for DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV-150mV)/1 V/ns] 3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 and 65ps for DDR3-2133 to accommodate for the lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mV-125mV)/1V/ns].
[ Table 51 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC175 Threshold tIS, tIH Derating [ps] AC/DC based Alternate AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CLK,CLK Differential Slew Rate 4.0 V/ns tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 3.0 V/ns tIS 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 96 67 8 6 2 -3 -9 -27 -54 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 104 75 16 14 10 5 -1 -19 -46 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 112 83 24 22 18 13 7 -11 -38 tIH 74 58 24 20 14 8 -2 -16 -36 1.2V/ns tIS 120 91 32 30 26 21 15 -2 -30 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 128 99 40 38 34 29 23 5 -22 tIH 100 84 50 46 40 34 24 10 -10
- 52 -
K4B1G0446G K4B1G0846G
datasheet
CLK,CLK Differential Slew Rate 4.0 V/ns 3.0 V/ns tIS 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 83 58 8 8 8 8 7 -2 -17 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 91 66 16 16 16 16 15 6 -9 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 99 74 24 24 24 24 23 14 -1 tIH 74 58 24 20 14 8 -2 -16 -36
Rev. 1.01
DDR3 SDRAM
[ Table 52 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based - Alternate AC150 Threshold tIS, tIH Derating [ps] AC/DC based Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV 1.2V/ns tIS 107 82 32 32 32 32 31 22 7 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 115 90 40 40 40 40 39 30 15 tIH 100 84 50 46 40 34 24 10 -10
tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 75 50 0 0 0 0 -1 -10 -25
tIH 50 34 0 -4 -10 -16 -26 -40 -60
[ Table 53 ] Derating values DDR3-1866 tIS/tIH-AC/DC based Alternate AC135 Threshold tIS, tIH Derating [ps] AC/DC based Alternate AC125 Threshold -> VIH(AC) = VREF(DC) + 135mV, VIL(AC) = VREF(DC) - 135mV CLK,CLK Differential Slew Rate 4.0 V/ns tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 68 45 0 2 3 6 9 5 -3 tIH 50 34 0 -4 -10 -16 -26 -40 -60 3.0 V/ns tIS 68 45 0 2 3 6 9 5 -3 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 68 45 0 2 3 6 9 5 -3 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 76 53 8 10 11 14 17 13 6 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 84 61 16 18 19 22 25 21 14 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 92 69 24 26 27 30 33 29 22 tIH 74 58 24 20 14 8 -2 -16 -36 1.2V/ns tIS 100 77 32 34 35 38 41 37 30 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 108 85 40 42 43 46 49 45 38 tIH 100 84 50 46 40 34 24 10 -10
- 53 -
K4B1G0446G K4B1G0846G
datasheet
CLK,CLK Differential Slew Rate 4.0 V/ns 3.0 V/ns tIS 63 42 0 4 6 11 16 15 13 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 63 42 0 4 6 11 16 15 13 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 71 50 8 12 14 19 24 23 21 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 79 58 16 20 22 27 32 31 29 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 87 66 24 28 30 35 40 39 37 tIH 74 58 24 20 14 8 -2 -16 -36
Rev. 1.01
DDR3 SDRAM
[ Table 54 ] Derating values DDR3-1866 tIS/tIH-AC/DC based - Alternate AC125 Threshold tIS, tIH Derating [ps] AC/DC based Alternate AC125 Threshold -> VIH(AC) = VREF(DC) + 125mV, VIL(AC) = VREF(DC) - 125mV 1.2V/ns tIS 95 74 32 36 38 43 48 47 45 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 103 82 40 44 46 51 56 55 53 tIH 100 84 50 46 40 34 24 10 -10
tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 63 42 0 4 6 11 16 15 13
tIH 50 34 0 -4 -10 -16 -26 -40 -60
[ Table 55 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition Slew Rate[V/ns]
>2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5
tVAC @175mV [ps] min
75 57 50 38 34 29 22 13 0 0
tVAC @150mV [ps] min
175 170 167 163 162 161 159 155 150 150
tVAC @135mV [ps] min
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
tVAC @125mV [ps] min
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
max
-
max
-
max
-
max
-
- 54 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS tDS VDDQ tDH tDS tVAC tDH
VIH(AC) min VREF to ac region VIH(DC) min nominal slew rate VREF(DC) nominal slew rate VIL(DC) max VREF to ac region VIL(AC) max tVAC VSS
TF
Setup Slew Rate = VREF(DC) - VIL(AC)max Falling Signal TF
TR
Setup Slew Rate V (AC)min - VREF(DC) = IH Rising Signal TR
Figure 21. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock).
- 55 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS VDDQ tDS tDH tDS tDH
VIH(AC) min
VIH(DC) min dc to VREF region VREF(DC) nominal slew rate dc to VREF region nominal slew rate
VIL(DC) max
VIL(AC) max
VSS
TR
Hold Slew Rate VREF(DC) - VIL(DC)max Rising Signal = TR
TF
Hold Slew Rate VIH(DC)min - VREF(DC) = Falling Signal TF
Figure 22. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock).
- 56 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS VDDQ tDS tDH nominal line VREF to ac region VIH(DC) min tangent line VREF(DC) tangent line VIL(DC) max VREF to ac region VIL(AC) max nominal line VSS tDS tVAC tDH
VIH(AC) min
tVAC
TR
tangent line[VIH(AC)min - VREF(DC)] Setup Slew Rate = Rising Signal TR
TF
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max] Falling Signal = TF Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock)
- 57 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS tDS VDDQ tDH tDS tDH
VIH(AC) min
nominal line
VIH(DC) min dc to VREF region VREF(DC) dc to VREF region VIL(DC) max tangent line tangent line
nominal line
VIL(AC) max
VSS
TR
tangent line [ VREF(DC) - VIL(DC)max ] Hold Slew Rate Rising Signal = TR
TF
tangent line [ VIH(DC)min - VREF(DC) ] Hold Slew Rate Falling Signal = TF Figure 24. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock)
- 58 -
K4B1G0446G K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
14.4 Data Setup, Hold and Slew Rate Derating :
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see Table 56) to the tDS and tDH (see Table 55) derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max (see Figure 25). If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(DC) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 27). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC) (see Figure ). If the actual signal is always later than the nominal slew rate line between shaded 'dc level to VREF(DC) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 28). For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 56). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [ Table 56 ] Data Setup and Hold Base-Values [ps] tDS(base) AC175 tDS(base) AC150 tDS(base) AC135 tDH(base) DC100 DDR3-800 75 125 150 DDR3-1066 25 75 100 DDR3-1333 30 65 DDR3-1600 10 45 DDR3-1866 0 20 reference VIH/L(AC) VIH/L(AC) VIH/L(AC) VIH/L(DC)
NOTE : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
[ Table 57 ] Derating values DDR3-800/1066 tDS/tDH - (AC175) tDS, tDH Derating in [ps] AC/DC based1 DQS,DQS Differential Slew Rate 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns tDS tDH tDS tDH tDS tDH tDS tDH 88 50 88 50 59 34 59 34 67 42 0 0 0 0 8 8 16 16 -2 -4 -2 -4 6 4 14 12 -6 -10 2 -2 10 6 -3 -8 5 0 -1 -10 -
DDR3 DQ Slew 800/ rate 1066 V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
4.0 V/ns tDS tDH 88 50 59 34 0 0 -
1.4V/ns tDS tDH 22 20 18 14 13 8 7 -2 -11 -16 -
1.2V/ns tDS tDH 26 24 21 18 15 8 -2 -6 -30 -26
1.0V/ns tDS tDH 29 34 23 24 6 10 -22 -10
NOTE : 1. Cell contents shaded in red are defined as 'not supported'.
[ Table 58 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - (AC150) tDS, tDH Derating in [ps] AC/DC based1 DQS,DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns tDS tDH tDS tDH tDS tDH tDS tDH 75 50 50 34 58 42 0 0 8 8 16 16 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 8 -8 16 0 24 8 15 -10 23 -2 14 -16 -
DQ Slew rate V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
4.0 V/ns tDS tDH 75 50 50 34 0 0 -
3.0 V/ns tDS tDH 75 50 50 34 0 0 0 -4 -
1.2V/ns tDS tDH 32 24 32 18 31 8 22 -6 7 -26
1.0V/ns tDS tDH 40 34 39 24 30 10 15 -10
NOTE : 1. Cell contents shaded in red are defined as 'not supported'.
- 59 -
K4B1G0446G K4B1G0846G
datasheet
3.0 V/ns tDS tDH 68 50 45 34 0 0 2 -4 tDS, tDH Derating in [ps] AC/DC based1 DQS,DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns tDS tDH tDS tDH tDS tDH tDS tDH 68 50 45 34 53 42 0 0 8 8 16 16 2 -4 10 4 18 12 26 20 3 -10 11 -2 19 6 27 14 14 -8 22 0 30 8 25 -10 33 -2 29 -16 -
Rev. 1.01
DDR3 SDRAM
[ Table 59 ] Derating values for DDR3-1866 tDS/tDH - (AC135)
DQ Slew rate V/ns
2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4
4.0 V/ns tDS tDH 68 50 45 34 0 0 -
1.2V/ns tDS tDH 35 24 38 18 41 8 37 -6 30 -26
1.0V/ns tDS tDH 46 34 49 24 45 10 38 -10
NOTE : 1. Cell contents shaded in red are defined as 'not supported'.
[ Table 60 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition Slew Rate[V/ns]
>2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5
tVAC[ps] DDR3-1066 (AC175) min
75 57 50 38 34 29 22 13 0 0
tVAC[ps] DDR3-1066/1333/1600 (AC150) min
175 170 167 163 162 161 159 155 155 150
tVAC[ps] DDR3-1866 (AC135) min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD max -
max
-
max
-
- 60 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS tDS VDDQ tDH tDS tVAC tDH
VIH(AC) min VREF to ac region VIH(DC) min nominal slew rate VREF(DC) nominal slew rate VIL(DC) max VREF to ac region VIL(AC) max tVAC VSS
TF
Setup Slew Rate = VREF(DC) - VIL(AC)max Falling Signal TF
TR
Setup Slew Rate V (AC)min - VREF(DC) = IH Rising Signal TR
Figure 25. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock).
- 61 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS VDDQ tDS tDH tDS tDH
VIH(AC) min
VIH(DC) min dc to VREF region VREF(DC) nominal slew rate dc to VREF region nominal slew rate
VIL(DC) max
VIL(AC) max
VSS
TR
Hold Slew Rate VREF(DC) - VIL(DC)max Rising Signal = TR
TF
Hold Slew Rate V (DC)min - VREF(DC) = IH Falling Signal TF
Figure 26. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock).
- 62 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS VDDQ tDS tDH nominal line VREF to ac region VIH(DC) min tangent line VREF(DC) tangent line VIL(DC) max VREF to ac region VIL(AC) max nominal line VSS tDS tVAC tDH
VIH(AC) min
tVAC
TR
tangent line[VIH(AC)min - VREF(DC)] Setup Slew Rate = Rising Signal TR
TF
tangent line[VREF(DC) - VIL(AC)max] Setup Slew Rate Falling Signal = TF Figure 27. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock)
- 63 -
K4B1G0446G K4B1G0846G
datasheet
tIS CK tIH tIS tIH
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
CK DQS
DQS tDS VDDQ tDH tDS tDH
VIH(AC) min
nominal line
VIH(DC) min dc to VREF region VREF(DC) dc to VREF region VIL(DC) max tangent line tangent line
nominal line
VIL(AC) max
VSS
TR
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] Rising Signal = TR
TF
Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ] Falling Signal = TF Figure 28. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock)
- 64 -

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